The present invention is directed to electronic devices and, more particularly, to repairable electronic devices that include redundant cells for replacing defective cells, such as are used in semiconductor memory devices.
Semiconductor memory devices, such as dynamic random access memory devices (DRAMs), typically include a semiconductor memory cell array formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
When data stored in one of the memory cells is read onto one of the bit lines, for example, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell which form a bit line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
As the capacity of semiconductor memory devices increases, the likelihood that a device includes one or more defective memory cells also increases, thereby adversely affecting the yield of the semiconductor memory device manufacturing processes. To address this problem, redundant memory cells are provided which can replace memory cells that are found to be defective during device testing. Typically, one or more spare rows, known as row redundancy, and/or one or more spare columns, known as column redundancy, are included in the memory cell array. The spare rows and/or columns have programmable decoders that can be programmed to respond to the address of the defective row and/or column while at the same time disabling the selection of the defective cell. The address of the defective memory cell is programmed into the fuse programmable decoder by blowing one or more appropriate fuses in a redundancy control circuit. When an address corresponding to a defective memory cell is received, the redundant memory cell is selected so that the word line or bit line that is connected to the redundant memory cell is substituted for the word line or bit line that is connected to the defective memory cell. As a result, the repaired memory device chip cannot be readily distinguished, at least electrically, from a defect-free chip.
To read the address of the defective memory cell stored in the fuses, at least one fuse latch is required to read and store the state of each fuse. Because the column and row addresses of current DRAM memory circuits may be thirteen bits or more, thirteen fuses or more and thirteen or more fuse latches may be needed to define the row address of a defective memory cell. As a result, the area of the support section of the memory device is significantly increased to store all of the redundancy information.
Alternatively, fewer fuses and fuse latches are used and represent only the most significant bits of the column address of the defective cell. As an example, the 10 most significant bits of a thirteen bit address are stored as fuses and readout by the fuse latches, and the least significant 3 bits are not stored. As a result, the column address stored by the fuses represents not only the column address of the defective memory cell but also represents up to 8 columns that have addresses with the same 10 most significant bits. As a result, not only is the column having defective cell replaced by a redundant column, but all 8 columns of cells are replaced by redundant columns.
To improve the granularity of the redundant memory cells, namely to decrease the number of redundant memory cells that must be used when a defective memory cell is to be replaced, each column of the array is divided by dividing the array into sub-arrays, and row address information representing the sub-array of the defective memory cell is applied to the output of the fuse latches. However, additional latches are required to read the additional data. Moreover, two pre-charge and readout cycles are required to read both sets of fuse latches.
It is therefore desirable to provide redundant bit lines with improved granularity in a manner that requires fewer fuse latches and fewer pre-charge/readout cycles.
The present invention provides a circuit and a method for providing column redundancy of a DRAM circuit by reading the values stored in the fuses that represent the row address of a failed memory cell only when the row address is to be read so that fewer fuse latches are required and only one pre-charge/readout cycle is needed.
In accordance with an aspect of the invention, address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the plurality of fuses to a corresponding latch circuit. The latch circuit is operable to receive fail address bit values from at least two of the plurality of fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.
In accordance with another aspect of the invention, a circuit delivers address information representing failed elements in an array portion of a device. A plurality of fuses are each operative to store a respective fail address bit value. Plural signal lines are each associated with a respective value of a portion of a further address. A plurality of switches each have an input terminal coupled to a corresponding fuse, a control terminal coupled to an associated signal line, and an output terminal. One or more latch circuits have a first input coupled to the output of at least two of the switches and an second input coupled to a pre-charge line. When a signal is delivered over a respective signal line to the gate terminal of the associated switch, one of the fail address bit values is delivered from one of the two or more fuses to the first input of the latch circuit. When a pre-charge signal is then delivered over the pre-charge line to the second input of the latch circuit, the fail address bit value is outputted by the latch circuit.
In accordance with a further aspect of the invention, a memory circuit includes a memory array, a control circuit operable to receive at least one row address value and at least one column address value, a word line controller operable to receive the row address value from the control circuit and to activate a row of the memory array corresponding to the row address value, a bit line controller operable to receive the column address value from the control circuit, a generator circuit operable to receive the row address value from the control circuit and to generate a further value based on a portion of the row address value, and a fuse latch circuit. The fuse latch circuit includes a plurality of fuses each operative to store a respective fail address bit value, a plurality of signal lines each associated with a respective one of the further values, a plurality of switches each having an input terminal coupled to a corresponding one of the plurality of fuses as well as a control terminal coupled to an associated one of the plurality of signal lines and an output terminal, and a plurality of latch circuits each of which has a first input coupled to the output of at least a corresponding two of the plurality of switches and a second input coupled to a pre-charge line. When a signal is delivered over a respective signal line to each gate terminal of associated ones of the switches, a respective fail address bit value is delivered to the first input of each of the latch circuits from one of its corresponding fuses. When a pre-charge signal is then delivered over the pre-charge line to each second input of the latch circuits, each of the latch circuits delivers its respective fail address bit value to the bit line controller. The bit line controller activates a column of the memory array corresponding to the column address value when a fail address comprised of the fail address bit values differs from the column address value. The bit line controller actives a redundant column line of the memory array when the fail address is the column address value.
The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings.